International Journal of Science, Engineering and Computer Technology

Parmeela Pachar ¹, Suman Rani ¹, Jai Parkash Godara ¹

Affiliations
1 Department of Electronics and Communication, PPIMT, Hisar, Haryana, IN

Abstract

Since there are many advancement in the VLSI technology and there are many efficient styles of designing VLSI circuits like CMOS, PTL, CPL, TG etc. In this paper GDI technique is described. This technique helps in designing low power digital combinatorial circuits by which we can eradicate the demerits of CMOS, TG techniques. Half subtractor using this technique is designed and presented in this paper. This consumes less power in comparison to CMOS and TG techniques. The proposed half subtractor circuit consists of 6 transistors. The circuit is designed and simulated using DSCH 3.5 and MICROWIND 3.5 on 45 nm. The proposed circuit has been compared with respect to the transistor count, area and power dissipation with the CMOS and TG technique.

Keywords

CMOS, GDI, PTL, Low Power, Digital Design.

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Priti Sindhu ¹, Suman Rani ¹

Affiliations
1 Department of Electronics and Communication, PPIMT, Hisar, Haryana, IN

Abstract

This paper, presents the design of CMOS based J-K flip-flop and ECRL (Efficient Charge Recovery Logic) based inverter and basic AND logic gate using adiabatic technique. The ECRL is more suitable for the design of flip-flops and sequential circuits, as it uses fewer transistors than the conventional CMOS implementation and other adiabatic techniques. Design of ECRL based adiabatic J-K flip-flop using MICROWIND 3.5 tool with 25 nm technology is also proposed. VERILOG simulations show that the energy loss of the adiabatic circuits is greatly reduced as compared to the conventional CMOS implementation.

Keywords

CMOS Digital Circuits, Adiabatic Circuits, ECRL, Flip-Flops, Power Dissipation.

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